The Skyscraper Era: Why AI Chips Are Growing Up, Not Out
The fundamental constraint of artificial intelligence is no longer just code or data—it is physics
For decades, the semiconductor industry followed a simple trajectory: making transistors smaller to fit more power onto a single slice of silicon. Moore’s Law was the guiding principle: shrink the components, increase performance, reduce cost. The strategy powered everything from personal computers to smartphones and cloud computing.
But AI has disrupted that model. Training and running modern AI systems requires enormous amounts of computation, far beyond what traditional chip scaling can deliver. The processors behind today’s most powerful AI models have grown so large and complex that they are running into a physical barrier inside semiconductor manufacturing: the reticle limit—the maximum area that can be patterned onto a chip during lithography.
In practical terms, this means the industry can no longer simply build a single, ever-larger processor.
“The era of the monolithic chip is over. We are now in the era of adaptive computing where chiplets and 3D packaging are the only way to keep pace with the massive performance requirements of AI.”
Lisa Su
CEO, Advanced Micro Devices (AMD)
Su’s observation captures a profound architectural shift now underway across the semiconductor industry. Instead of designing one giant processor, engineers increasingly break systems into multiple smaller chips—known as chiplets—that can be connected together inside a single package. These components may include logic processors, specialized accelerators, memory modules and networking chips.
In other words, the industry is moving away from flat chips toward vertically integrated systems. The metaphor many engineers now use is architectural: chips are no longer single-story houses but skyscrapers—complex, multi-layered structures where each level performs a different function.
The change is driven largely by artificial intelligence. Modern AI accelerators must process massive volumes of data while constantly communicating with high-bandwidth memory. That requirement has pushed designers toward stacking memory chips directly above processors, reducing the physical distance data must travel and dramatically increasing performance.
But building these “skyscraper chips” introduces a new challenge. The bottleneck is no longer just how precisely circuits can be printed onto silicon. It is how precisely those chips can be connected, stacked and integrated.
The New Battleground: Advanced Packaging
For decades, semiconductor packaging was a relatively mundane part of the manufacturing process. Once a chip was fabricated, it was simply enclosed in protective material and wired to the outside world. The real innovation—and most of the value—lay in the chip itself.
AI has changed that equation.
When multiple processors and memory stacks must operate as a unified system, the quality of their interconnections becomes critical. Nanometer-scale bonding, ultra-fast interconnects and precise alignment are now essential to ensure that stacked chips behave like a single computing engine.
The industry refers to these techniques collectively as advanced packaging.
“It’s no longer about the chip; it’s about the data center as a single unit of computing. Advanced packaging is the bridge that turns individual pieces of silicon into a cohesive AI supercomputer.”
Jensen Huang
CEO, NVIDIA
Huang’s comment reflects how AI has reshaped the hierarchy of computing. Instead of thinking about individual chips, engineers increasingly design entire systems—servers, accelerators and memory stacks—as integrated platforms. Advanced packaging acts as the connective tissue that binds those components together.
This shift is already visible in the world’s most powerful AI processors. The latest GPUs combine massive logic chips with stacks of high-bandwidth memory, all connected through sophisticated packaging technologies developed by manufacturers such as Taiwan Semiconductor Manufacturing Company and memory suppliers like SK Hynix.
These systems can contain multiple chiplets arranged side by side, stacked vertically or interconnected through advanced substrates. The architecture resembles a miniature data center compressed into a single package.
The consequence is clear: as chip design becomes more modular and vertically integrated, the competitive frontier is shifting. The next decade of semiconductor innovation may be determined less by lithography alone and more by the tools used to assemble these complex structures.
And that shift has opened a strategic opportunity for a company that already sits at the center of the global chipmaking ecosystem.
ASML’s Quiet Expansion
For more than a decade, ASML has dominated one of the most critical technologies in semiconductor manufacturing: extreme ultraviolet lithography or EUV.
EUV machines use highly specialized optics and powerful light sources to project microscopic circuit patterns onto silicon wafers. These systems—among the most complex machines ever built—are essential for manufacturing the world’s most advanced processors. Companies such as Intel and Taiwan Semiconductor Manufacturing Company rely on them to produce cutting-edge chips for AI, smartphones and high-performance computing.
The Netherlands-based company is effectively the sole supplier of EUV systems, giving it enormous influence over the global semiconductor supply chain.
But the shift toward AI architectures is pushing the industry into new territory.
“While lithography remains our core, the complexity of next-generation AI hardware requires a holistic approach. We are increasingly looking at how our technology can enable the high-precision interconnects required for advanced 3D stacking.”
Christophe Fouquet
CEO, ASML
Fouquet’s remarks signal a broader strategic ambition. If advanced packaging becomes the next critical stage in semiconductor manufacturing, the machines used to enable that process could become just as important as lithography itself.
ASML already possesses many of the capabilities required to enter this domain. Its expertise in optics, precision positioning, wafer handling and inspection technologies can potentially be adapted to machines that help align and connect stacked chips with extreme accuracy.
The company has begun exploring systems designed to support advanced memory manufacturing and next-generation chip architectures. Internally, engineers are also investigating how artificial intelligence can optimize the control software that governs these complex tools—allowing machines to operate faster and detect manufacturing defects earlier in the production process.
In essence, ASML appears to be positioning itself not only as the company that prints the circuits of the future, but also as one that could help assemble them.
The Next Phase of AI Hardware
The economic implications of this shift are significant.
According to semiconductor research firm Yole Group, the market for advanced packaging technologies is expected to grow steadily over the coming decade, with particularly strong demand driven by AI processors and high-bandwidth memory systems. As chip architectures become more modular, the importance—and value—of the tools used to integrate them is likely to increase.
This dynamic mirrors earlier phases of the semiconductor industry. Historically, the companies that controlled the most critical manufacturing tools often captured a disproportionate share of the industry’s value.
Lithography was one such inflection point. As chipmakers pushed toward smaller and smaller transistor geometries, the complexity of lithography systems increased dramatically. ASML’s dominance in EUV technology allowed it to become one of the most strategically important firms in the global technology ecosystem.
Advanced packaging may represent the next such frontier.
If the future of AI hardware lies in stacked architectures and interconnected chiplets, the precision tools required to build those systems will become essential infrastructure. The companies that supply those tools could wield enormous influence over the pace—and direction—of technological progress.
For ASML, the opportunity is clear.
The era of printing ever-smaller transistors is not over. But as AI pushes computing into new physical limits, the next phase of innovation may depend less on shrinking circuits and more on building upward—turning chips into skyscrapers of silicon.
And in that vertical future, the machines that assemble those structures may prove just as important as the ones that created them.
Credit:
Illustration: Altair Media
Caption:
AI chips are increasingly built as stacked “skyscrapers” of silicon rather than single monolithic processors.
